1. Field of the Invention
The field of the invention relates to interrupts occurring during data processing and in particular, to detecting and transmitting interrupts to a processor.
2. Description of the Prior Art
Data processors which are operable to perform a plurality of functions are known. Generally, data processors that can run multiple functions have the ability to interrupt a function that is being processed at a particular moment and start processing a different higher priority one. This enables the latency associated with a high priority task to be reduced. In order to signal to the processor that a higher priority task is awaiting processing interrupt signals are used.
If a peripheral, for example, has a high priority task that it wishes the processor to perform it will send an interrupt signal to the processor to indicate to the processor that it has a task that it needs it to perform. If the core is processing an interruptible task, then it will take the interrupt and suspend processing of its current task and commence processing of the task specified by the interrupt. In order to notify the peripheral that it has taken the task, it will send a “taken” signal to the peripheral. When processing is complete, then it sends a “return” signal to the peripheral indicating that processing of the task is complete and that the interrupt has been dealt with and the processor then resumes processing the interrupted task. The peripheral issuing the interrupt will reset its interrupt request signal once it has detected that the interrupt has been taken and the core is dealing with its request. Clearly this resetting of the signal will not be immediate as it takes time both for the processor to send the taken signal and for the peripheral to react to it.
When processing interrupts, it is important that while the interrupt is being processed by the core, any new interrupts received are detected. The interrupt signal having an asserted value IRQ is not necessarily an indication of a new interrupt being received as it may simply mean that the interrupt request currently being processed has not yet been reset. Thus, while the core is processing an interrupt, it is changes in the interrupt signal IRQ that are important and signal a new interrupt to be processed, not the value of the IRQ signal itself. In other words, deassertion and then reassertion of this signal need to be detected to indicate that an interrupt is to be processed.
When an interrupt is not currently being processed by the core, then it is the value of this signal, i.e. its level that is important and indicates whether there is an interrupt to be processed or not.
FIG. 1 shows an interrupt detection circuit according to the prior art. In this circuit an interrupt request signal IRQ is received and is passed through a flip flop 10. Flip flop 10 acts to delay the signal by a clock cycle. The value output by flip flop 10 is then compared to the input interrupt request signal IRQ received and if there is a difference in the signals, this indicates that there has been a change in value in the interrupt request signal during the last clock signal and in response to this the signal IRQ-pend indicating that there is an interrupt request pending is asserted.
There is also a level signal input to this circuit and this is used to indicate when it is the level of the signal that it is important to detect rather than a change in its value. In this embodiment when the level signal is set to 1, IRQ is output as IRQ-pend via output flip flop 20. When level is set to 0 the delayed value of IRQ is compared with the current value of IRQ and thus, changes in the value are detected.
Conventional interrupt detecting circuits such as that shown in FIG. 1 are able to detect both edges and levels of a signal so as to provide the core with suitable interrupt requests.